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Mohammad Asyaei

Assistant Professor of Electronic Engineering

Education

  • Ph.D. 2008-2013

    Electronic Engineering

    Ferdowsi University of Mashhad, Mashhad, Iran

  • M.Sc. 2002-2004

    Electronic Engineering

    Ferdowsi University of Mashhad, Mashhad, Iran

  • B.Sc. 1998-2002

    Electronic Engineering

    Amirkabir University of Technology, Tehran, Iran

Teaching

  • Digital systems I, II
  • Electronic I, II, III
  • Electric circuits I, II
  • Pulse techniques
  • Switching power supply
  • Digital VLSI design
  • Linear integrated circuits

Selected Publications

Asyaei, M., Moradi, F. A domino circuit technique for noise-immune high fan-in gates (2018) Journal of Circuits, Systems and Computers, 27 (10), art. no. 1850151, .

DOI: 10.1142/S0218126618501517

Noise immunity is an important concern in deep nano-scale technologies, especially for high fan-in gates. In this paper, a new domino circuit technique is proposed by which the noise immunity of high fan-in gates increases while the power consumption reduces. The proposed technique is based on the comparison of two currents, which vary with respect to the voltage across the pull-down network (PDN). By comparing these currents, the voltage level of the dynamic node is pulled up or pulled down depending on the input voltages. Using this technique, the voltage swing on the PDN can be decreased to reduce the power consumption. Moreover, a diode-connected NMOS transistor is added in series with the PDN in the proposed technique. This will result in reducing the subthreshold leakage current due to the stacking effect and, as a result, the noise immunity will improve. To demonstrate the efficacy of the proposed domino design over the conventional techniques, high fan-in gates are designed and compared in 90nm CMOS technology. Simulation results exhibit at least 1.87X noise immunity improvement and 20% power consumption reduction in comparison to the standard footless domino (SFLD) circuits at the same delay. © 2018 World Scientific Publishing Company.

AUTHOR KEYWORDS: Domino logic; high fan-in gate; noise immunity
INDEX KEYWORDS: Electric power utilization; Leakage currents; Nanotechnology; Timing circuits, Conventional techniques; Domino Logic; High fan-in; NMOS transistors; Noise immunity; Power consumption reduction; Pull down networks; Sub-threshold leakage currents, Delay circuits
PUBLISHER: World Scientific Publishing Co. Pte Ltd

Asyaei, M. A new circuit scheme for wide dynamic circuits (2018) International Journal of Engineering, Transactions B: Applications, 31 (5), pp. 699-704.

DOI: 10.5829/ije.2018.31.04a.03

In this paper, a new circuit scheme is proposed to reduce the power consumption of dynamic circuits. In the proposed circuit, an NMOS keeper transistor is used to maintain the voltage level in the output node against charge sharing, leakage current and noise sources. Using the proposed keeper scheme, the voltage swing on the dynamic node is lowered to reduce the power consumption of wide fan-in gates. Furthermore, the subthreshold leakage current is decreased by using the footer transistor in diode configuration and consequently, the noise immunity is increased in the proposed circuit. Simulation results of wide fan-in OR gates in 90nm CMOS technology demonstrate 48% power reduction and 1.65× noise-immunity improvement at the same delay compared to the conventional dynamic circuit for 32-bit OR gates. © 2018 Materials and Energy Research Center. All Rights Reserved.

AUTHOR KEYWORDS: Dynamic circuit; Keeper; Leakage current; Noise immunity; Wide fan-in gates
INDEX KEYWORDS: Electric power utilization; Leakage currents; Timing circuits, Dynamic Circuits; Keeper; Keeper transistor; Noise immunity; Power reductions; Sub-threshold leakage currents; Voltage levels; Wide fan-in, Delay circuits
PUBLISHER: Materials and Energy Research Center

Asyaei, M. A new low-power dynamic circuit for wide fan-in gates (2018) Integration, the VLSI Journal, 60, pp. 263-271.

DOI: 10.1016/j.vlsi.2017.10.010

In this paper, a new dynamic circuit is proposed to reduce the power consumption of wide fan-in gates. Since the voltage difference across the pull-down network determines the output in the proposed circuit, the voltage swing on the pull-down network can be lowered to decrease the dramatically increasing power consumption of wide fan-in gates. Wide fan-in OR gates are designed and simulated using the proposed domino circuit in 90 nm CMOS technology. Simulation results exhibit up to 2.62X improvement in noise immunity and 44% reduction in power consumption compared to the conventional domino circuits at the same delay. Moreover, a 2-read, 1-write ported 64-word × 32-bit/word register file is designed using the proposed domino circuit. The Register file is simulated using low-Vth 90 nm CMOS model in all process corners. The results shows 25% power reduction and 32% speed improvement for the proposed register file in comparison with the conventional register file at the same noise margin floor. © 2017 Elsevier B.V.

AUTHOR KEYWORDS: Dynamic circuit; Noise immunity; Register file; Wide fan-in gates
INDEX KEYWORDS: CMOS integrated circuits; Delay circuits; Electric power utilization; Timing circuits, Dynamic Circuits; Noise immunity; Power reductions; Pull down networks; Register files; Speed improvement; Voltage difference; Wide fan-in, Low power electronics
PUBLISHER: Elsevier B.V.

Asyaei, M., Ebrahimi, E. Low power dynamic circuit for power efficient bit lines (2018) AEU - International Journal of Electronics and Communications, 83, pp. 204-212.

DOI: 10.1016/j.aeue.2017.08.048

In this paper, a low power dynamic circuit is presented to reduce the power consumption of bit lines in multi-port memories. Using the proposed circuit, the voltage swing of the pull-down network is lowered to reduce the power consumption of wide fan-in gates employed in memory's bit lines. Wide fan-in OR gates are designed and simulated using the proposed dynamic circuit in 90 nm CMOS technology. Simulation results show at least 40% reduction of power consumption and 1.2X noise immunity improvement compared to the conventional dynamic circuits at the same delay. Exploiting the proposed dynamic circuit, wide fan-in multiplexers are also designed. The multiplexers are simulated using a 90 nm CMOS model in all process corners. The results show 41% power reduction and 27% speed improvement for the proposed 128-input multiplexer in comparison with the conventional multiplexer at the same noise immunity. © 2017 Elsevier GmbH

AUTHOR KEYWORDS: Bit lines; Dynamic logic; Noise immunity; Wide fan-in gates
INDEX KEYWORDS: CMOS integrated circuits; Delay circuits; Electric power utilization; Multiplexing equipment; Timing circuits, Bit lines; Dynamic Circuits; Dynamic logic; Multi-port memory; Noise immunity; Pull down networks; Speed improvement; Wide fan-in, Low power electronics
PUBLISHER: Elsevier GmbH

Asyaei, M. A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology (2015) Integration, the VLSI Journal, 51, art. no. 1127, pp. 61-71.

DOI: 10.1016/j.vlsi.2015.06.003

In this paper, a new leakage-tolerant domino circuit is presented which has lower power consumption and higher noise immunity without significant delay increment for wide fan-in gates. The main idea in the proposed circuit is using sense amplifier for sensing the difference between voltages across the pull down network (PDN). This strategy provides correct output. In the proposed technique, therefore, the voltage swing of the dynamic node can be reduced to decrease the power consumption caused by the heavy switching capacitance in wide fan-in gates. The simulation is provided with 64-bit wide OR gates using a 90 nm CMOS technology model. The simulation results are compared with that of standard domino circuits at the same delay, and 35% power consumption reduction and 2.31× noise-immunity improvement are observed. © 2015 Elsevier B.V.

AUTHOR KEYWORDS: Domino logic; Leakage current; Noise immunity; Sense amplifier; Wide fan-in gates
INDEX KEYWORDS: Capacitance; CMOS integrated circuits; Delay circuits; Electric power utilization; Leakage currents, Deep sub-micron technology; Domino Logic; Lower-power consumption; Noise immunity; Power consumption reduction; Pull down networks; Sense amplifier; Wide fan-in, Amplifiers (electronic)
PUBLISHER: Elsevier

Asyaei, M., Peiravi, A. Low power wide gates for modern power efficient processors (2014) Integration, the VLSI Journal, 47 (2), pp. 272-283.

DOI: 10.1016/j.vlsi.2013.08.005

In this paper, a low power register file and tag comparator is proposed which has lower leakage and higher noise immunity without dramatic speed degradation due to the wide fan-in gates. Simulation of register files and tag comparators designed is done using low-Vth 90 nm CMOS process technology model in all process corners. The results demonstrate 20% power reduction and 2× noise-immunity improvement in the implemented register file using the proposed circuit at the same delay compared to the standard domino circuits. On the other hand, simulation of tag comparators implemented using the other proposed circuit shows 41%, 22% and 7.5% reduction in power, delay and area, respectively compared to the standard footless domino at the same robustness condition. Moreover, the register file and the tag comparator designed with the proposed circuits respectively show 2.48 and 3 times improvement in the defined figure of merit compared to the counterpart circuits designed with the conventional domino circuit. Thus, the proposed are power efficient and suitable approaches for embedded processors with multi-ported register file and fully-associative caches with large number of tag comparators. © 2013 Elsevier B.V.

AUTHOR KEYWORDS: Cache; Domino logic; Register file; Tag comparator; Wide fan-in
INDEX KEYWORDS: Cache; Domino Logic; Embedded processors; Figure of merits; Power efficient; Power reductions; Register files; Wide fan-in, CMOS integrated circuits; Computer simulation; Delay circuits, Comparators (optical)

Asyaei, M. A new coupling scheme for multiphase and quadrature signals generation (2012) Analog Integrated Circuits and Signal Processing, 73 (3), pp. 993-997.

DOI: 10.1007/s10470-012-9940-6

A new coupling technique for low-phase noise low-power quadrature signals generation is presented. In the proposed technique two identical CMOS LC-voltage-controlled oscillators (VCOs) are coupled in an in-phase anti-phase manner via the substrates of the MOS varactors. Use of substrates (in other words the intrinsic gate-bulk capacitances) of the MOS varactors for coupling, results in elimination of any extra coupling elements and also their associated noises. Utilizing the proposed technique, a quadrature VCO (QVCO) is designed and simulated in TSMC 0.18 lm RF-CMOS technology. The phase noise of the proposed LC-QVCO is -137.5 dBc/Hz at 3 MHz frequency offset from 5.4 GHz center frequency, while the total DC current drawn from a 1.8-V power supply is 8.37 mA. Generalizing the proposed coupling scheme to several identical LC-VCOs, low-phase noise multiphase signals can be generated. The proposed circuits can operate with power supplies as low as 0.6 V without any performance degradation. © Springer Science+Business Media, LLC 2012.

AUTHOR KEYWORDS: Cross-connected VCO; Multiphase; Phase noise; Quadrature
INDEX KEYWORDS: Capacitance; Circuit oscillations; CMOS integrated circuits; Frequency allocation; Oscillistors; Phase noise; Varactors, Coupling techniques; Frequency offsets; Multiphase; Multiphase signals; Performance degradation; Quadrature; Quadrature signal; RF CMOS technology, Variable frequency oscillators
PUBLISHER: Springer New York LLC

Asyaei, M., Ebrahimi, E. A low-phase noise injection-locked quadrature voltage-controlled oscillator (2012) Analog Integrated Circuits and Signal Processing, 71 (2), pp. 319-325.

DOI: 10.1007/s10470-011-9779-2

This article presents a low-phase noise quadrature voltage-controlled oscillator (QVCO) in which the re-filtering technique of the side-band noise is adopted. In the proposed QVCO, besides using re-filtering technique, the passive elements replaced the noisy and lossy active coupling devices. Therefore, due to the elimination of the associate noise sources of the active coupling devices and re-filtering of side-band noise of the circuit, the proposed QVCO shows an excellent phase-noise and FOM. The proposed QVCO was implemented and simulated in TSMC 0.18 lm RF-CMOS technology. The phase noise of the proposed QVCO at 3 MHz offset frequency from the 3 GHz center frequency is -144 dBc/Hz, for a current consumption of 11.5 mA at a power supply of 1.8-V. Simulation results show the proposed QVCO can operate with power supply as low as 0.6 V. Monte-Carlo analyses for, 3% device mismatch and process variation, result in phase error lower than 0.8°. Generalizing the proposed coupling technique to several core VCOs very low-phase noise multiphase signals can be generated.

AUTHOR KEYWORDS: Multiphase; Phase noise; Quadrature
INDEX KEYWORDS: CMOS integrated circuits; Oscillistors, Coupling techniques; Current consumption; Monte carlo analysis; Multiphase; Multiphase signals; Offset frequencies; Quadrature; Quadrature voltage controlled oscillator, Phase noise
PUBLISHER: Kluwer Academic Publishers

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