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Mahsa Mehrad

Associate Professor of Electronic Engineering

Education

  • Ph.D. 2010-2014

    Electronic Engineering

    Semnan University, Semnan, Iran

  • M.Sc. 2008-2010

    Electronic Engineering

    Semnan University, Semnan, Iran

  • B.Sc. 2003-2007

    Electronic Engineering

    Semnan University, Semnan, Iran

Teaching

  • Semiconductor Devices
  • Basic circuit theory I & II
  • Electronic I &II

Selected Publications

Mehrad, M. Three p-silicon layers in reliable lateral double diffused metal oxide semiconductor transistor (2018) 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018, 2018-January, pp. 1-4.

DOI: 10.1109/ULIS.2018.8354776

Inserting three p-layers in the drift region and buried oxide of the Lateral Double Diffused MOSFET (LDMOS) is the main goal of this paper. One of these layers is considered in the drift region and two others are in the buried oxide. Moreover, these layers have different lengths. The new structure helps to have high breakdown voltage and low on-resistance that improves Figure Of Merit (FOM) in this power transistor. Also, replacing p-silicon layer instead of silicon dioxide under the drift region reduces lattice temperature and helps to have a reliable device. The electrical parameters of the novel structure are compared with the conventional one using ATLAS simulator. © 2018 IEEE.

AUTHOR KEYWORDS: Breakdown voltage; LDMOS; Specific on-resistance; Temperature
INDEX KEYWORDS: Electric breakdown; Heterojunction bipolar transistors; Metals; Oxide semiconductors; Semiconducting silicon; Semiconductor junctions; Silica; Silicon on insulator technology; Temperature; Transistors, Electrical parameter; Figure of merit (FOM); High breakdown voltage; Lateral double diffused MOSFET; Lateral double-diffused metal oxide semiconductors; Lattice temperatures; LDMOS; Specific-on resistance, MOS devices
PUBLISHER: Institute of Electrical and Electronics Engineers Inc.

Mehrad, M., Zareiee, M., Orouji, A.A. Controlled Kink Effect in a Novel High-Voltage LDMOS Transistor by Creating Local Minimum in Energy Band Diagram (2017) IEEE Transactions on Electron Devices, 64 (10), art. no. 8026573, pp. 4213-4218.

DOI: 10.1109/TED.2017.2737531

A new technique to control the kink effect in the high-voltage lateral double-diffused MOSFET (LDMOS) is presented in this paper. This technique produces a local minimum in the band diagram of the proposed structure, which causes the lower barrier height for the holes from the channel to the source region. So, the produced excess holes during the impact ionization process in the channel are reduced significantly. We have called the proposed structure as local minimum energy band LDMOS (LMEB-LDMOS) transistor. The LMEB-LDMOS structure contains modified source and drain regions. The modified source region creates a local minimum in the energy band diagram for absorbing the excess holes, and the modified drain region causes high breakdown voltage (462 V) and low specific on-resistance ( 5.1mΩc cm2. Also, the drift region with lower doping density than drain is deleted in LMEB-LDMOS transistor. The simulation with 2-D ATLAS simulator shows that the proposed structure improves the device performance. © 1963-2012 IEEE.

AUTHOR KEYWORDS: Breakdown voltage; kink effect; lateral double-diffused MOSFET (LDMOS); on-resistance
INDEX KEYWORDS: Band structure; Electric breakdown; Heterojunction bipolar transistors; Impact ionization; MOSFET devices; Semiconductor junctions; Transport properties, Device performance; Energy-band diagram; High breakdown voltage; High voltage lateral double-diffused MOSFET; Kink effect; Lateral double diffused MOSFET; On-resistance; Specific-on resistance, MOS devices
PUBLISHER: Institute of Electrical and Electronics Engineers Inc.

Mehrad, M., Ghadi, E.S. C-shape silicon window nano MOSFET for reducing the short channel effects (2017) Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings, art. no. 7962572, pp. 164-167.

DOI: 10.1109/ULIS.2017.7962572

This paper introduces a novel reduced short channel effects in nanoscale SOI MOSFETs by C-shape silicon window inside the channel, source and buried oxide. This work investigates the main characterizations such as maximum lattice temperature, subthreshold swing, DIBL, threshold voltage roll-off which all of them show the superiority of the proposed structure compared to the conventional SOI MOSFET (C-MOSFET) in case of reliable low-voltage applications. All the achieved numerical results have been extracted by two-dimensional simulator ATLAS. © 2017 IEEE.

AUTHOR KEYWORDS: drain current; Maximum lattice temperature; MOSFET; Short channel effect; SOI
INDEX KEYWORDS: Drain current; Silicon; Silicon on insulator technology; Threshold voltage, Lattice temperatures; Low-voltage applications; MOS-FET; Numerical results; Short-channel effect; Silicon windows; Subthreshold swing; Threshold voltage roll-off, MOSFET devices
PUBLISHER: Institute of Electrical and Electronics Engineers Inc.

Zareiee, M., Mehrad, M. A reliable nano device with appropriate performance in high temperatures (2017) ECS Journal of Solid State Science and Technology, 6 (4), pp. M50-M54.

DOI: 10.1149/2.0281704jss

There are many problems during designing MOSFETs in nano scale regime. Some problems contain high gate current, high off current and high electron temperature. These problems are created when the peak of electric field is high which causes reducing the device reliability. So, reducing the peak of electric field can be an objective during designing a device. In this paper, a new structure for improvement of the partial SOI MOSFET parameters is presented. So, oxide layers are considered in the channel and in the extended drain region to reduce the peak of electric field. This reduction results in achieving reduced off current, gate current and electron temperature. The simulation with ATLAS simulator shows that the new structure has improved hot carrier effect and its reliability is more than conventional one. © 2017 The Electrochemical Society. All rights reserved.

INDEX KEYWORDS: Electron temperature; MOSFET devices; Nanotechnology, Device reliability; Drain region; Gate current; High temperature; Hot carrier effect; Off current; Oxide layer; Partial SOI, Electric fields
PUBLISHER: Electrochemical Society Inc.

Zareiee, M., Orouji, A.A., Mehrad, M. A novel high breakdown voltage LDMOS by protruded silicon dioxide at the drift region (2016) Journal of Computational Electronics, 15 (2), pp. 611-618.

DOI: 10.1007/s10825-015-0785-y

Breakdown voltage and specific on-resistance are two important parameters in lateral double diffused MOSFET (LDMOS) devices. In order to have a high breakdown voltage, the electric field profile should be uniform. In this paper a dual protruded silicon dioxide in the drift region of LDMOS (DP-LDMOS) is proposed which creates new peaks in the electric field profile and an improvement of the breakdown voltage. Also, a triple P window is considered between these protruded oxides to have the balanced charge in the drift region that helps to have a higher breakdown voltage than a conventional LDMOS transistor. The simulation with two-dimensional ATLAS simulator shows that the proposed DP-LDMOS structure has a low specific on-resistance due to incorporating the protruded oxides in the drift region. © 2016, Springer Science+Business Media New York.

AUTHOR KEYWORDS: Breakdown voltage; Lateral double diffused MOSFET (LDMOS); Specific on-resistance
INDEX KEYWORDS: Electric breakdown; Electric fields; MOS devices; MOSFET devices; Semiconductor junctions; Silica, Drift regions; Electric field profiles; High breakdown voltage; Lateral double diffused MOSFET; LDMOS transistors; Specific-on resistance, Heterojunction bipolar transistors
PUBLISHER: Springer New York LLC

Mehrad, M. Periodic trench region in LDMOS transistor: A new reliable structure with high breakdown voltage (2016) Superlattices and Microstructures, 91, pp. 193-200.

DOI: 10.1016/j.spmi.2015.12.041

A new device structure for high breakdown voltage and low maximum lattice temperature of the LDMOS device is proposed in this paper. The main idea in the proposed structure is using a Si3N4 trench region with open windows made by silicon in it. In the conventional structure, a trench oxide was used to have high breakdown voltage that causes high lattice temperature. So, replacing Si3N4 material is suitable way to have a more reliable device. The proposed periodic trench region in LDMOS transistor (PTR-LDMOS) has periodic open windows to increase the additional peaks in the electric field profile and increase the breakdown voltage. Also, the simulation with two-dimensional ATLAS simulator shows that reduced main electric field peaks cause low electron temperature that enhances the reliability of the proposed structure. © 2015 Elsevier Ltd. All rights reserved.

AUTHOR KEYWORDS: Breakdown voltage; Lattice temperature; LDMOS; Reliability
INDEX KEYWORDS: Electric breakdown; Electric fields; Heterojunction bipolar transistors; MOS devices; Reliability, Conventional structures; Electric field profiles; High breakdown voltage; Lattice temperatures; LDMOS; LDMOS devices; LDMOS transistors; Low electron temperature, Periodic structures
PUBLISHER: Academic Press

Mehrad, M. Application of N+ buried layer in reducing lattice temperature of nano-scale MOSFET (2016) ECS Journal of Solid State Science and Technology, 5 (12), pp. M158-M162.

DOI: 10.1149/2.0251612jss

In this paper a new technique for controlling lattice temperature is proposed. The main idea in the proposed structure is using three buried layers in the device. These layers are top buried oxide, down buried oxide and buried silicon. In this structure, the buried silicon is located between two insulator layers. The proposed structure which is called as Inserted silicon layer in buried oxide of the SOI-MOSFET (ISB-SOI) is simulated with two-dimensional ATLAS simulator. It is shown higher thermal conductivity of silicon than silicon-dioxide reduces maximum lattice temperature and self-heating effects in the nano-scale MOSFETs. Moreover, effective mobility, off current and sub-threshold swing improve in the proposed structure in comparison to Conventional SOI-MOSFET (C-SOI). © 2016 The Electrochemical Society. All rights reserved.

INDEX KEYWORDS: Nanotechnology; Silicon on insulator technology; Thermal conductivity, Buried layer; Buried oxides; Effective mobilities; Insulator layer; Lattice temperatures; Self-heating effect; Silicon layer; Subthreshold swing, MOSFET devices
PUBLISHER: Electrochemical Society Inc.

Mehrad, M. Omega shape channel LDMOS: A novel structure for high voltage applications (2016) Physica E: Low-Dimensional Systems and Nanostructures, 75, art. no. 12115, pp. 196-201.

DOI: 10.1016/j.physe.2015.09.016

A new device structure for high breakdown voltage and low specific on resistance of the LDMOS device is proposed in this paper. The main idea in the proposed structure is using omega shape channel. The benefits of omega shape channel could be determined by extending depletion region in the drift region that causes low specific on resistance. Also, uniform horizontal electric field would be achieved that results in high breakdown voltage. The proposed structure is called Omega-shape Channel LDMOS (OCH-LDMOS). The simulation with two dimensional ATLAS simulator shows that the breakdown voltage increases to 712 V from 243 V of the conventional LDMOS at 12 μm drift length. Also, effective values of doping, length, and depth of Omega-shape channel are investigated. © 2015 Elsevier B.V.

AUTHOR KEYWORDS: Breakdown voltage; Channel; LDMOS; Specific on resistance
INDEX KEYWORDS: Electric breakdown; Electric fields; Heterojunction bipolar transistors; Semiconductor junctions, Channel; Depletion region; High breakdown voltage; High voltage applications; Horizontal electric fields; LDMOS; Novel structures; Specific-on resistance, MOS devices
PUBLISHER: Elsevier

Mehrad, M. Reducing floating body and short channel effects in nano scale transistor: Inserted P+ Region SOI-MOSFET (2016) ECS Journal of Solid State Science and Technology, 5 (9), pp. M88-M92.

DOI: 10.1149/2.0251609jss

Short channel effects are the main challenges in nano scale devices. The novel way for controlling this problem is studied in this paper. Moreover, floating body effect is reduced significantly. The goal of this work is inserting P+ region in the active region and buried oxide. The P+ region is considered in the N+-source and the different doping of N+ and P+ which results in tunneling holes from valence band to conduction band. So, the accumulated holes in the channel reduces and floating body effect controls, effectively. In this case the potential between drain and left side of the channel decreases and DIBL reduces. Moreover, the simulation with ATLAS simulator shows that inserting P+ region in SOI-MOSFET (IPR-MOSFET) causes low lattice temperature and subthreshold swing in comparison to conventional SOI-MOSFET (C-MOSFET). So, the benefits of the proposed structure could be applicable in nano devices. © 2016 The Electrochemical Society.

INDEX KEYWORDS: MOS devices; Nanotechnology; Silicon on insulator technology; Threshold voltage, Active regions; Floating bodies; Floating body effect; Lattice temperatures; Nanoscale device; NanoScale Transistors; Short-channel effect; Subthreshold swing, MOSFET devices
PUBLISHER: Electrochemical Society Inc.

Mehrad, M., Zareiee, M. Improved device performance in nano scale transistor: An extended drain SOI MOSFET (2016) ECS Journal of Solid State Science and Technology, 5 (7), pp. M74-M77.

DOI: 10.1149/2.0231607jss

Reducing the size of SOI MOSFET especially in nano regime for applying them in Integrated Circuits is difficult, because of the important problems of Short Channel Effects (SCE). These effects reduce the reliability of the device and it is objective to decrease them. In this paper, the goal is to propose a new structure for SOI MOSFET to improve SCEs. In this case the, the form of drain and channel is changed to obtain more reliable device. In this case, the drain region is extended into the channel improving the performance of the device. The drain has higher doping concentration, which causes better performance. The simulation with two dimensional ATLAS simulator shows that the new structure has better performance than the conventional one in cases of off current, subthreshold slope, threshold voltage, DIBL, maximum electron temperature and drain current which leads to more reliable device. © 2016 The Electrochemical Society All rights reserved.

INDEX KEYWORDS: Drain current; Field effect transistors; Nanostructured materials; Nanotechnology; Threshold voltage, Device performance; Doping concentration; Drain region; NanoScale Transistors; Off current; Short-channel effect; SOI-MOSFETs; Subthreshold slope, MOSFET devices
PUBLISHER: Electrochemical Society Inc.

Mehrad, M. Thin layer oxide in the drift region of Laterally double-diffused metal oxide semiconductor on silicon-on-insulator: A novel device structure enabling reliable high-temperature power transistors (2015) Materials Science in Semiconductor Processing, 30, pp. 599-604.

DOI: 10.1016/j.mssp.2014.11.017

In this paper a new lateral double diffused metal oxide semiconductor (LDMOS) transistor on silicon-on-insulator (SOI) technology is reported. In the proposed structure a trench oxide in the drift region is reformed to reduce surface temperature. In the LDMOS devices one way for achieving high breakdown voltage is incorporating the trench oxide in the drift region. But, this strategy causes high lattice temperature in the device. So, the middle of the trench oxide in the drift region is etched and filled with the silicon to have higher thermal conductivity material and reduce the lattice temperature in the drift region. The simulation with two-dimensional ATLAS simulator shows that the novel thin trench oxide in the n-drift region of LDMOS transistor (TT-LDMOS) have lower maximum lattice temperature with an acceptable breakdown voltage in respect to the conventional LDMOS (C-LDMOS) structure with the trench oxide in the drift region. So, TT-LDMOS can be a reliable device for power transistors. © 2014 Elsevier Ltd. All rights reserved.

AUTHOR KEYWORDS: Breakdown voltage; LDMOS; Maximum lattice temperature; Mobility
INDEX KEYWORDS: Atmospheric temperature; Carrier mobility; Electric breakdown; Electric insulators; Heterojunction bipolar transistors; Metallic compounds; MOS devices; Power electronics; Semiconducting silicon; Silicon; Thermal conductivity; Transistors, High breakdown voltage; High-temperature power; Lateral double-diffused metal oxide semiconductors; Lattice temperatures; LDMOS; Metal oxide semiconductor; Siliconon-insulator technology (SOI); Surface temperatures, Silicon on insulator technology
PUBLISHER: Elsevier Ltd

Mehrad, M. Controlling floating body effect in high temperatures: L-shape SiGe region in nano-scale MOSFET (2015) Superlattices and Microstructures, 85, pp. 573-580.

DOI: 10.1016/j.spmi.2015.06.023

In this paper a new technique for controlling floating body effect and self-heating effects is proposed. The main idea in the proposed structure is using a L-shape SiGe region in the nano-scale SOI-MOSFET (LS-SOI). The L-shape SiGe region is located in the source region and is extended under channel. The difference band gap between silicon and silicon-germanium cause discontinuity in band diagram which helps to collect channel holes. Reducing the hole density in channel of the proposed LS-SOI in comparison to conventional SOI-MOSFET (C-SOI) results in suppressed floating body effect. Also, the SiGe region under the channel decreases the lattice temperature in the LS-SOI. Replacing the SiGe with higher thermal capability than buried oxide is useful to have a reliable structure. Moreover, effective mobility, off current and sub-threshold swing improves in the proposed structure. © 2015 Elsevier Ltd. All rights reserved.

AUTHOR KEYWORDS: Floating body effect; Lattice temperature; Parasitic BJT; SOI
INDEX KEYWORDS: BiCMOS technology; Energy gap; Heterojunction bipolar transistors; MOSFET devices; Nanotechnology; Silicon on insulator technology, Effective mobilities; Floating body effect; Lattice temperatures; Parasitic BJT; Self-heating effect; Silicon Germanium; SOI; Subthreshold swing, Silicon alloys
PUBLISHER: Academic Press

Mehrad, M., Orouji, A.A., Taheri, M. A new technique in LDMOS transistors to improve the breakdown voltage and the lattice temperature (2015) Materials Science in Semiconductor Processing, 34, pp. 276-280.

DOI: 10.1016/j.mssp.2015.02.057

Abstract A new technique for high breakdown voltage of the LDMOS device is proposed in this paper. The main idea in the proposed technique is to insert the P+ silicon windows in the buried oxide at the interface of the n-drift to improve the breakdown voltage, electric field and maximum lattice temperature. The proposed structure is called as P+ window LDMOS (PW-LDMOS). It is shown by extending the depletion region between the P+ windows and the n-drift region, the breakdown voltage of PW-LDMOS increases to 405 V from 84V of the conventional LDMOS on 1 μm silicon layer and 2 μm buried oxide layer. Also, effective values of doping, length, and depth of P+ window are investigated in the breakdown voltage. Moreover, a self-heating-effect is alleviated by the silicon windows in comparison with the conventional LDMOS. All the achieved results have been extracted by two-dimensional and two-carriers simulator ATLAS. © 2015 Elsevier Ltd. All rights reserved.

AUTHOR KEYWORDS: Breakdown voltage; LDMOS; Self-heating effects; SOI
INDEX KEYWORDS: BiCMOS technology; Electric breakdown; Electric fields; Heterojunction bipolar transistors; Silicon; Silicon on insulator technology, Buried oxide layers; Depletion region; High breakdown voltage; Lattice temperatures; LDMOS; LDMOS transistors; Self-heating effect; SOI, MOS devices
PUBLISHER: Elsevier Ltd

Orouji, A.A., Mehrad, M. Positive charges at buried oxide interface of RESURF: An analytical model for the breakdown voltage (2014) Superlattices and Microstructures, 72, pp. 336-343.

DOI: 10.1016/j.spmi.2014.05.002

A new analytical model of reduced surface field (RESURF) transistor on silicon-on-insulator (SOI) technology with positive charges at the buried oxide interface is proposed. Interface charges at the interface of the buried oxide (BOX) and drift region increase the electric field in the BOX and decrease the surface electric field in the silicon region. So, this approach is suitable to enhance the breakdown voltage with increasing the electric field at the BOX. Two-dimensional Poisson equation is solved for the new structure and surface potential, surface electric field and breakdown voltage are derived. Moreover, the validity of this novel model is demonstrated by comparing with numerical simulation of ATLAS simulator. The influence of drift region doping, density of positive charges at the buried oxide interface and also the thicknesses of field oxide and BOX are discussed in this paper. Furthermore, the analytical results have the best agreement with numerical simulation. © 2014 Elsevier Ltd. All rights reserved.

AUTHOR KEYWORDS: Analytical model; Breakdown voltage; Electric field; RESURF
INDEX KEYWORDS: Analytical models; Electric breakdown; Electric fields; Numerical models; Two dimensional; Analytical models; Electric breakdown; Electric fields; Electric insulators; Numerical models; Poisson equation; Silicon; Surface potential, Analytical results; Buried oxides; Interface charge; Positive charges; Reduced surface field (RESURF); RESURF; Siliconon-insulator technology (SOI); Surface electric fields, Electric insulators; Silicon on insulator technology
PUBLISHER: Academic Press

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