FORGOT YOUR DETAILS?

Meysam Zareiee

Assistant Professor of Electronic Engineering

Education

  • Ph.D. 2009-2014

    Electronic Engineering

    Semnan University, Semnan, Iran

  • M.Sc. 2007-2009

    Electronic Engineering

    Semnan University, Semnan, Iran

  • B.Sc. 2003-2007

    Electronic Engineering

    Semnan University, Semnan, Iran

Selected Publications

Zareiee, M. A novel dual trench gate power device by effective drift region structure (2019) Superlattices and Microstructures, 125, pp. 8-15.

DOI: 10.1016/j.spmi.2018.10.019

In this paper, a new double trench-gate LDMOS transistor is presented obtaining desirable trade-off between breakdown voltage and specific on-resistance. Three silicon layers with two silicon dioxide layers are inserted in the drift region under the P-well. The silicon layers with high doping densities help to have low specific on-resistance. Moreover, the silicon dioxide layers modify the electric field and increase the breakdown voltage. The simulation of the proposed Double oxide and N– type silicon windows in drift region of the double gate trench MOSFET (DONW-DG) with two dimensional ATLAS simulator shows that the electrical characteristics of the new structure are better than conventional trench gate LDMOS (TG) and conventional dual trench gate LDMOS (DG). Also, the design consideration is done to have optimum values of the lengths and thicknesses of the layers. In the optimum values, the breakdown voltage of about 209 V and the specific on-resistance of 0.51 mΩ cm2 cause acceptable figure of merit. © 2018 Elsevier Ltd

AUTHOR KEYWORDS: Breakdown voltage; LDMOS transistor; Semicnductor devices; Silicon on insulator; Specific on-resistance
INDEX KEYWORDS: Economic and social effects; Electric breakdown; Electric insulators; MOS devices; MOSFET devices; Semiconductor junctions; Silica; Silicon on insulator technology, Design considerations; Doping densities; Electrical characteristic; Figure of merits; LDMOS transistors; Semicnductor devices; Silicon dioxide layers; Specific-on resistance, Power semiconductor devices
PUBLISHER: Academic Press

Zareiee, M., Salami, H. Inserting PN junction in a power device for achieving improved figure of merit (2018) 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018, 2018-January, pp. 1-4.

DOI: 10.1109/ULIS.2018.8354777

Lateral double diffused metal oxide semiconductor field effect transistors (LDMOS) in silicon on insulator (SOI) technology are widely applied in power applications. The breakdown voltage is high in these devices. In this paper a new LDMOS is presented to improve the performance achieving more reliable device. The idea is based on considering two silicon layers (P-type and N-type) in drift and insulator regions, respectively. The simulation with two dimensional ATLAS simulator shows that the breakdown voltage is increased. Moreover, the specific on-resistance and lattice temperature are improved. So, the Figure Of Merit (FOM) is significantly improved. © 2018 IEEE.

AUTHOR KEYWORDS: Breakdown voltage; Lateral Double diffused Metal Oxide Field Effect Transistor; Lattice temprature; Silicon On Insulator
INDEX KEYWORDS: Electric breakdown; Electric insulators; Metallic compounds; Metals; MOS devices; MOSFET devices; Oxide semiconductors; Power semiconductor devices; Semiconductor junctions; Transistors, Figure of merit (FOM); Lateral double-diffused metal oxide; Lateral double-diffused metal oxide semiconductors; Lattice temperatures; Lattice temprature; P type and N types; Power applications; Specific-on resistance, Silicon on insulator technology
PUBLISHER: Institute of Electrical and Electronics Engineers Inc.

Mehrad, M., Zareiee, M., Orouji, A.A. Controlled Kink Effect in a Novel High-Voltage LDMOS Transistor by Creating Local Minimum in Energy Band Diagram (2017) IEEE Transactions on Electron Devices, 64 (10), art. no. 8026573, pp. 4213-4218.

DOI: 10.1109/TED.2017.2737531

A new technique to control the kink effect in the high-voltage lateral double-diffused MOSFET (LDMOS) is presented in this paper. This technique produces a local minimum in the band diagram of the proposed structure, which causes the lower barrier height for the holes from the channel to the source region. So, the produced excess holes during the impact ionization process in the channel are reduced significantly. We have called the proposed structure as local minimum energy band LDMOS (LMEB-LDMOS) transistor. The LMEB-LDMOS structure contains modified source and drain regions. The modified source region creates a local minimum in the energy band diagram for absorbing the excess holes, and the modified drain region causes high breakdown voltage (462 V) and low specific on-resistance ( 5.1mΩc cm2. Also, the drift region with lower doping density than drain is deleted in LMEB-LDMOS transistor. The simulation with 2-D ATLAS simulator shows that the proposed structure improves the device performance. © 1963-2012 IEEE.

AUTHOR KEYWORDS: Breakdown voltage; kink effect; lateral double-diffused MOSFET (LDMOS); on-resistance
INDEX KEYWORDS: Band structure; Electric breakdown; Heterojunction bipolar transistors; Impact ionization; MOSFET devices; Semiconductor junctions; Transport properties, Device performance; Energy-band diagram; High breakdown voltage; High voltage lateral double-diffused MOSFET; Kink effect; Lateral double diffused MOSFET; On-resistance; Specific-on resistance, MOS devices
PUBLISHER: Institute of Electrical and Electronics Engineers Inc.

Zareiee, M., Abtin, M. A reliable high performance nano SOI MOSFET by considering quadruple silicon zones (2017) Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings, art. no. 7962563, pp. 208-211.

DOI: 10.1109/ULIS.2017.7962563

A novel nano MOSFET is reported in this paper to have high electrical performance. In the proposed structure which is named as QSZ-MOSFET, two silicon zones are considered in the channel and buried oxide. The N-silicon zone in the channel region creates a depletion region that increases the current capability. Moreover, the majority of the holes due to the floating body effect could be absorbed in this N-silicon region. The P-silicon zone in the buried oxide helps to reduce the lattice temperature and creates a way for heat transfer from the active region to the substrate. The proposed structure and conventional MOSFET are simulated with ATLAS simulator and shows the benefits of the QSZ-MOSFET in nano-meter regime. © 2017 IEEE.

AUTHOR KEYWORDS: Floating body effect; Maximum lattice temprature; MOSFET; SOI
INDEX KEYWORDS: Heat transfer; Silicon; Silicon on insulator technology; Substrates, Current capability; Depletion region; Electrical performance; Floating body effect; Lattice temperatures; Maximum lattice temprature; MOS-FET; Nano-meter regimes, MOSFET devices
PUBLISHER: Institute of Electrical and Electronics Engineers Inc.

Zareiee, M. High performance nano device with reduced short channel effects in high temperature applications (2017) ECS Journal of Solid State Science and Technology, 6 (7), pp. M75-M78.

DOI: 10.1149/2.0101707jss

Solving the problem of short channel effects in Metal Oxide Semiconductor Field effect transistors is an important challenge of electronic industry. Moreover, self heating and hot carrier effects are major problems in the devices based on Silicon on Insulator technology. In this paper, a new structure is proposed to overcome the mentioned problems. So, a P+ region is considered in bottom of the source region and is extended into the buried oxide region. Moreover, a HfO2 window is considered in border of source and channel region. This strategy helps to increase the device performance and obtain more reliable device. The proposed transistor is simulated using ATLAS simulator and the results shows that the proposed structure has acceptable behavior comparing to the conventional one. © 2017 The Electrochemical Society.

INDEX KEYWORDS: Hafnium oxides; High temperature applications; Metals; MOS devices; MOSFET devices; Problem solving; Silicon on insulator technology; Threshold voltage; Transistors, Buried oxides; Channel region; Device performance; Electronic industries; Hot carrier effect; Self-heating; Short-channel effect; Source region, Field effect transistors
PUBLISHER: Electrochemical Society Inc.

Zareiee, M., Mehrad, M. A reliable nano device with appropriate performance in high temperatures (2017) ECS Journal of Solid State Science and Technology, 6 (4), pp. M50-M54.

DOI: 10.1149/2.0281704jss

There are many problems during designing MOSFETs in nano scale regime. Some problems contain high gate current, high off current and high electron temperature. These problems are created when the peak of electric field is high which causes reducing the device reliability. So, reducing the peak of electric field can be an objective during designing a device. In this paper, a new structure for improvement of the partial SOI MOSFET parameters is presented. So, oxide layers are considered in the channel and in the extended drain region to reduce the peak of electric field. This reduction results in achieving reduced off current, gate current and electron temperature. The simulation with ATLAS simulator shows that the new structure has improved hot carrier effect and its reliability is more than conventional one. © 2017 The Electrochemical Society. All rights reserved.

INDEX KEYWORDS: Electron temperature; MOSFET devices; Nanotechnology, Device reliability; Drain region; Gate current; High temperature; Hot carrier effect; Off current; Oxide layer; Partial SOI, Electric fields
PUBLISHER: Electrochemical Society Inc.

Zareiee, M., Orouji, A.A. Superior electrical characteristics of novel nanoscale MOSFET with embedded tunnel diode (2017) Superlattices and Microstructures, 101, pp. 57-67.

DOI: 10.1016/j.spmi.2016.11.022

Metal Oxide Semiconductor Field Effect Transistors (MOSFET) play an important role in electronic industry development. To improve the electrical characteristics of these transistors in this paper, a new structure is proposed to reduce floating body effect, lattice temperature, and short channel effects. The main mechanism for controlling these critical issues is using an embedded tunnel diode. The tunnel diode formed by heavily doped N and P silicon windows which are embedded into the buried oxide layer. The accumulated holes are effectively released by the tunnel current of the tunnel diode. The simulation with ATLAS simulator shows that the proposed structure works properly and the important parameters such as subthreshold slope, off current, voltage gain, and maximum lattice temperature improve in comparison with the conventional nanoscale MOSFET. © 2016 Elsevier Ltd

AUTHOR KEYWORDS: Floating body effect; Metal Oxide Semiconductor Field Effect Transistor; Self heating effect; Short channel effects; Silicon On Insulator
INDEX KEYWORDS: Dielectric devices; Diodes; Electric breakdown; Electron beam lithography; Field effect transistors; Metallic compounds; Metals; MOS devices; Nanotechnology; Oxide semiconductors; Semiconducting silicon; Semiconductor diodes; Silicon on insulator technology; Threshold voltage; Transistors; Tunnel diodes, Buried oxide layers; Electrical characteristic; Electronic industries; Floating body effect; Lattice temperatures; Self-heating effect; Short-channel effect; Subthreshold slope, MOSFET devices
PUBLISHER: Academic Press

Zareiee, M., Orouji, A.A., Mehrad, M. A novel high breakdown voltage LDMOS by protruded silicon dioxide at the drift region (2016) Journal of Computational Electronics, 15 (2), pp. 611-618.

DOI: 10.1007/s10825-015-0785-y

Breakdown voltage and specific on-resistance are two important parameters in lateral double diffused MOSFET (LDMOS) devices. In order to have a high breakdown voltage, the electric field profile should be uniform. In this paper a dual protruded silicon dioxide in the drift region of LDMOS (DP-LDMOS) is proposed which creates new peaks in the electric field profile and an improvement of the breakdown voltage. Also, a triple P window is considered between these protruded oxides to have the balanced charge in the drift region that helps to have a higher breakdown voltage than a conventional LDMOS transistor. The simulation with two-dimensional ATLAS simulator shows that the proposed DP-LDMOS structure has a low specific on-resistance due to incorporating the protruded oxides in the drift region. © 2016, Springer Science+Business Media New York.

AUTHOR KEYWORDS: Breakdown voltage; Lateral double diffused MOSFET (LDMOS); Specific on-resistance
INDEX KEYWORDS: Electric breakdown; Electric fields; MOS devices; MOSFET devices; Semiconductor junctions; Silica, Drift regions; Electric field profiles; High breakdown voltage; Lateral double diffused MOSFET; LDMOS transistors; Specific-on resistance, Heterojunction bipolar transistors
PUBLISHER: Springer New York LLC

Zareiee, M. Modifying buried layers in nano-MOSFET for achieving reliable electrical characteristics (2016) ECS Journal of Solid State Science and Technology, 5 (10), pp. M113-M117.

DOI: 10.1149/2.0151610jss

In this paper, a new nano-scale SOI MOSFET is proposed to improve the critical electrical characteristics. In the proposed modified buried layers SOI MOSFET (MB-MOSFET), three different layers are considered under the active region. A U-shape P silicon window, N+ buried layer and SiO2 window under the channel region. Applying the materials with higher thermal conductivity than silicon dioxide reduces maximum temperature and controls self heating effects, significantly. Also, a new diode creates between N+ source region and P silicon window that reduces the majority of the holes in the channel and causes controlled floating body effect. Also, the simulation with two dimensional ATLAS simulator shows that the mobility increases which causes higher drain current in the MB-MOSFET as it is compared to the Conventional MOSFET (C-MOSFET). © 2016 The Electrochemical Society.

INDEX KEYWORDS: Drain current; Nanotechnology; Silica; Silicon on insulator technology; Silicon oxides; Thermal conductivity, Active regions; Channel region; Different layers; Electrical characteristic; Floating body effect; Maximum temperature; Self-heating effect; Silicon windows, MOSFET devices
PUBLISHER: Electrochemical Society Inc.

Mehrad, M., Zareiee, M. Improved device performance in nano scale transistor: An extended drain SOI MOSFET (2016) ECS Journal of Solid State Science and Technology, 5 (7), pp. M74-M77.

DOI: 10.1149/2.0231607jss

Reducing the size of SOI MOSFET especially in nano regime for applying them in Integrated Circuits is difficult, because of the important problems of Short Channel Effects (SCE). These effects reduce the reliability of the device and it is objective to decrease them. In this paper, the goal is to propose a new structure for SOI MOSFET to improve SCEs. In this case the, the form of drain and channel is changed to obtain more reliable device. In this case, the drain region is extended into the channel improving the performance of the device. The drain has higher doping concentration, which causes better performance. The simulation with two dimensional ATLAS simulator shows that the new structure has better performance than the conventional one in cases of off current, subthreshold slope, threshold voltage, DIBL, maximum electron temperature and drain current which leads to more reliable device. © 2016 The Electrochemical Society All rights reserved.

INDEX KEYWORDS: Drain current; Field effect transistors; Nanostructured materials; Nanotechnology; Threshold voltage, Device performance; Doping concentration; Drain region; NanoScale Transistors; Off current; Short-channel effect; SOI-MOSFETs; Subthreshold slope, MOSFET devices
PUBLISHER: Electrochemical Society Inc.

Zareiee, M. A novel high performance nano-scale MOSFET by inserting Si3N4 layer in the channel (2015) Superlattices and Microstructures, 88, pp. 254-261.

DOI: 10.1016/j.spmi.2015.09.017

In this paper a novel feature of a nano-scale SOI-MOSFET is presented. The goal of the proposed Si3N4 Layer SOI-MOSFET (SL-SOI) is inserting a Si3N4 layer in the channel region. This layer in the channel region which has different band gap than silicon causes uniform electric field. So, hot carrier effect and gate current are controlled sufficiently. Moreover, Si3N4 layer in the channel is extended in the buried oxide to reduce the lattice temperature, and sub-threshold slope. The proposed structure is simulated with two-dimensional ATLAS simulator and compared with conventional SOI-MOSFET. The results show that the new device has a high performance which expands nano-scale MOSFET applications in high temperature. © 2015 Elsevier Ltd. All rights reserved.

AUTHOR KEYWORDS: Electric field; Hot carrier effect; Si3N4 layer; SOI-MOSFET
INDEX KEYWORDS: Electric fields; Energy gap; High temperature applications; Hot carriers; Nanotechnology; Silicon; Silicon on insulator technology, Buried oxides; Channel region; High temperature; Hot carrier effect; Lattice temperatures; SOI-MOSFETs; Subthreshold slope; Uniform electric fields, MOSFET devices
PUBLISHER: Academic Press

Dideban, A., Zareiee, M., Orouji, A.A. A simple petri net controller by solving some integer linear programming problems (2014) Control Engineering and Applied Informatics, 16 (4), pp. 3-11.

The number of control places for designing a simple Petri Net controller is important. So, many efforts have been accomplished during last decade to design a controller with small number of such places. But, the number after applying some of these methods is still large and some of the other methods are complicated. In this paper, we have attempted to develop the previous methods for obtaining a simple controller in a systematic way. In this method, a small number of control places are obtained by solving a few numbers of Integer Linear Programming Problems at which the numbers of constraints and variables in each problem smoothly grow with respect to the numbers of reachable states. Also, the obtained controller model is maximally permissive.

AUTHOR KEYWORDS: Control place; Discrete event system; Integer linear programming problem; Petri net; Supervisory control
PUBLISHER: Control Engineering and Applied Informatics Journal

TOP